instruction address register — komandų skaitiklis statusas T sritis automatika atitikmenys: angl. command counter; control counter; control register; instruction address register; instruction counter; operation address register; program counter; program address counter;… … Automatikos terminų žodynas
instruction counter — komandų skaitiklis statusas T sritis automatika atitikmenys: angl. command counter; control counter; control register; instruction address register; instruction counter; operation address register; program counter; program address counter;… … Automatikos terminų žodynas
Instruction level parallelism — (ILP) is a measure of how many of the operations in a computer program can be performed simultaneously. Consider the following program: 1. e = a + b 2. f = c + d 3. g = e * fOperation 3 depends on the results of operations 1 and 2, so it cannot… … Wikipedia
Instruction Pointer — [dt. Befehlszeiger] (auch EIP, extended Instruction Pointer), dasjenige Register des Prozessors, das die Speicheradresse des nächsten auszuführenden Maschinenbefehls enthält. Nachdem der Prozessor eine Anweisung abgearbeitet hat, lädt er den… … Universal-Lexikon
Register renaming — In computer engineering, register renaming refers to a technique usedto avoid unnecessary serialization of program operations imposed by the reuseof registers by those operations.Problem definitionPrograms are composed of instructions which… … Wikipedia
Register machine — In mathematical logic and theoretical computer science a register machine is a generic class of abstract machines used in a manner similar to a Turing machine. All the models are Turing equivalent. Contents 1 Overview 2 Formal definition 3 … Wikipedia
Instruction set — An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception… … Wikipedia
Instruction cycle — An instruction cycle (sometimes called fetch and execute cycle, fetch decode execute cycle, or FDX) is the basic operation cycle of a computer. It is the process by which a computer retrieves a program instruction from its memory, determines what … Wikipedia
Instruction pipeline — Pipelining redirects here. For HTTP pipelining, see HTTP pipelining. Basic five stage pipeline in a RISC machine (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back). In the fourth clock… … Wikipedia
Instruction scheduling — In computer science, instruction scheduling is a compiler optimization used to improve instruction level parallelism, which improves performance on machines with instruction pipelines. Put more simply, without changing the meaning of the code, it … Wikipedia
Instruction Set Architecture — Eine Befehlssatzarchitektur (engl. Instruction Set Architecture, kurz: ISA) ist – vereinfacht gesagt – die formale Spezifikation bestimmter Verhaltensweisen eines Prozessors aus Sicht seines Programmierers, auf die sich dieser bei der… … Deutsch Wikipedia
